Got interested in the recent Spider WIP improvements and the correlated Table Tennis Championship development, I’ve decided to take a look at this exotic FPGA-based video blitter.
The thing is definitely weird, as Haze also explained in his blog it basically reads an i/o port to enter into “blitter mode”, and any following write to the memory mapped bus actually routes to the blitter, and using the address bus instead of the data bus either for obfuscation or performance reasons.
It’s not a novelty (Sharp X1 Japanese computer line did something similar back in 1981) but definitely a bit annoying, and the main roadblock towards emulation of this game until today: